The present invention relates generally to analog to digital signal converters and, more particularly, to such converters using a successive approximation conversion method.
Successive approximation methods of analog to digital conversion are well-known in the art for producing accurate and relatively high speed digital conversion. Generally, prior art converters using this method compare an unknown analog input signal to one or more precisely known reference signals in a series of digit generating comparison steps. In each step, the relative magnitudes of the analog input signal and the reference signal are compared and an error or difference signal is generated which is compared with another reference signal during the next succeeding step. Each such comparison step provides a digit of the final output signal in descending digital order until the desired level of quantization is reached.
A typical prior art successive approximation analog to digital (A/D) converter is shown in FIG. 1. An analog input signal is applied to comparator means 10 along input line 11. Comparator means 10 outputs a signal to clock and control logic means 20 which controls an internal successive approximation register 30 for producing digital outputs as a function of the output signals from comparator means 10. The digital outputs from successive approximation register 30 activate the bits in internal digital to analog (D/A) converter means 40, which has a known internal reference voltage applied thereto. The output from D/A converter means 40 is also applied to comparator means 10. The signal from comparator means 10 to clock and logic control means 20 represents the difference between the analog input signal and the analog output signal from internal D/A converter means 40.
Conversion is initiated by an externally supplied pulse to clock and logic control means 20. All bits except the most significant bit (MSB) are initially turned off. Control logic means 20 then sets one bit at a time in successive approximation register 30 in either a high or low state depending upon the output of comparator means 10. The MSB is initially set high, corresponding to a logical 1 and, thus, D/A converter means 40 produces an analog signal equal to one-half full scale. The output signal from D/A converter means 40 is compared to the input signal along line 11 at summing junction 12. If the former signal is less than the input signal, comparator means 10 causes successive approximation register 30 to leave the MSB at logical 1 and, as the clock continues, bit 2 (MSB-1) is also set at logical 1. If the signal output from D/A converter means 40 is greater than the input signal, the MSB is reset to logical 0 before proceeding to bit 2. Any succeeding bit that does not cause the combined bit currents' output from D/A converter means 40 to exceed the input signal remains set at logical 1, and any bit that causes the combined bit output signal from D/A converter means 40 to exceed the input signal is reset to a logical 0. After the final, or least significant bit (LSB) has been tried, successive approximation register 30 transmits a conversion complete signal. The output of successive approximation register 30 at this time is a digital number representing the analog input as a fraction of the internal reference voltage applied to D/A converter means 40.
Typically in such prior art successive approximation converters, each comparison decision made during the conversion is irrevocable. This means that the digits, once set within the successive approximation register, cannot be changed. Incorrect digits resulting from an erroneous comparison degrades the accuracy of the total output conversion signal. Incorrect comparisons may result from limitations in the comparison circuits themselves, such as transient recovery and response or static accuracy limitations, or by transient errors in the circuits which supply the comparison circuits with the reference voltages to be compared. While some A/D converters in the prior art do include a means of correcting an erroneous digital count, these usually require complicated signal amplifiers and track and hold circuits which increase the cost of production and significantly slow down conversion time.
The speed of successive approximation converters is determined by the amount of time required for the execution of each comparison step. Generally, sufficient time must be allowed prior to the next comparison to permit the transient errors of the circuit to settle out to a necessary minimum level so that an accurate comparison can be made. For converters digitizing to an N bit digital number, N periods of settling are required. Of the three basic components in these converters, the successive approximation register, the D/A converter, and the comparator, the settling time of the D/A converter and the comparator combination to better than one-half bit accuracy, the typically desired level, usually determines the time for each period. For example, if the D/A converter and comparator settle to one-half bit accuracy in one microsecond per period for a 12 bit converter, then the total minimum conversion time is approximately 12 microseconds.
Since it is generally desirable to decrease the conversion time and increase the speed of operation of such converters, several attempts have been made in the prior art to decrease the settling time allowed for each bit level. However, simply reducing the settling time at each bit level will compromise the conversion accuracy.
It is known to use two step or course/fine conversion techniques to increase the conversion speed, but only at a cost of significantly increased circuit complexity. In such two step processes, the digital bits are tried in two groups by separate A/D converter means. Conversion speed is increased because each set of bits may be successively approximated simultaneously and the settling time for each bit is reduced since less accuracy is required.
It is also known to increase conversion speed by employing multiple settling clocks, different for each bit level of successive approximation. However, this again substantially increases the circuit complexity and cost, as opposed to circuits using a single settling time clock for all bit levels.
Further, it has been suggested to employ multi step conversion techniques through a single set of successive approximation register hardware with a single settling time clock in order to get N bit accuracy from hardware elements scaled for significantly less than N bits. However, such circuits emphasize accuracy considerations and are not concerned with increasing the conversion speed of a system already maintaining N bit accuracy, nor do they suggest means to compensate for conversion errors experienced in speeding up the conversion time.
Thus, there exists a need for a new successive approximation A/D converter which permits the conversion time to be significantly reduced without increasing successive approximation register complexity and yet maintaining conversion accuracy within a desired level.